Not applicable.
Not applicable.
(1) Field of the Invention
The present invention generally relates to semiconductor devices. More particularly, this invention relates to a programmable memory transistor having a floating gate that exhibits improved voltage retention.
(2) Description of the related art
Programmable memory transistors (PMT), including electrically programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices, are a type of insulated gate field effect transistor (IGFET) having nonvolatile memory. As used in the art, xe2x80x9cnonvolatilexe2x80x9d refers to the retention of memory without the need of a power source, here by trapping a charge on a xe2x80x9cfloatingxe2x80x9d gate disposed above the IGFET channel region and typically below a conventional control gate electrode, such that the control and floating gates are xe2x80x9cstacked.xe2x80x9d The floating gate is described as xe2x80x9cfloatingxe2x80x9d because it is electrically insulated from the channel region by a gate oxide, typically insulated from the control gate by a xe2x80x9ctunnelxe2x80x9d oxide, and not directly accessed by any electrical conductor. PMT""s can be electrically programmed after manufacture by placing an electrical charge on the floating gate by the effects of tunneling or avalanche injection from the control gate electrode through the tunnel oxide. Once an electrical charge is placed on the floating gate, the charge is trapped there until it is deliberately removed, such as by exposure to ultraviolet light. The trapped charge on the PMT floating gate raises the threshold voltage of the underlying channel region of the IGFET, thus raising the xe2x80x9cturn onxe2x80x9d voltage of the IGFET to a value above the voltage otherwise required for the IGFET. Accordingly, the IGFET stays xe2x80x9coffxe2x80x9d even when a normal turn-on voltage is applied to its control gate electrode.
Stacked control and floating gates require two separate conductor layers, typically polysilicon, resulting in a double-polysilicon (xe2x80x9cPoly1/Poly2xe2x80x9d) device structure. PMT""s are typically fabricated in the same semiconductor substrate as MOS (metal-oxide-semiconductor) transistors, which are single-polysilicon layer structures and therefore require fewer patterning steps than PMT""s. Therefore, PMT""s have been proposed that make use of a single polysilicon layer, such as that disclosed in U.S. Pat. No. 6,324,097. An example of another single-polysilicon PMT is shown in FIG. 1, in which a PMT 110 is fabricated on a semiconductor substrate 112 doped with an N-type impurity. A P-well 114 is formed in a surface region of the substrate 112, and divided by a field oxide 116 into two active regions. An NMOS transistor 118 is formed in one of the active regions and conventionally includes source and drain regions 120 and 122 in the P-well 114, a channel 124 between the source and drain regions 120 and 122, and a gate electrode 126 separated from the channel 124 by a gate insulator 128 (e.g., silicon dioxide). Source and drain metal 130 and 132 make ohmic contact with the source and drain regions 120 and 122, respectively. The gate electrode 126 of the NMOS transistor 118 is a floating gate, in that it is not directly connected to a gate metal or other conductor. Instead, the gate electrode 126 is defined by a single polysilicon layer that also defines a second floating gate 146 of a control gate structure 138 fabricated in the second active region of the substrate 112 (on the right-hand side of FIG. 1). The control gate structure 138 represented in FIG. 1 includes two N+ contact diffusions 142 within an N-well 144 (though a single contact diffusion 142 or more than two contact diffusions 142 could be present). The N-well 144 serves as the control gate of the control gate structure 138, effectively replacing the second polysilicone layer of a conventional double-polysilicon PMT. The control gate (N-well) 144 is separated from the second floating gate 146 by a gate oxide 148, creating what is effectively a coupling capacitor. A control gate metal 150 contacts the N+ contact diffusions 142 to provide ohmic contact with the control gate 144.
When programming the prior art PMT 110, an electrical charge is placed on the floating gate 126 of the NMOS transistor 118 by the effect of tunneling or avalanche injection from the channel 124 of the gate electrode 126 through the gate insulator 128 to the floating gate 126. For this purpose, a sufficiently high potential must be applied to the control gate metal 150 to capacitively induce a charge in the floating gate 146 as well as the floating gate 126 as a result of the gates 126 and 146 being formed of the same polysilicon layer. Simultaneously, the drain region 122 is biased at a high voltage level while the source region 120 and substrate 112 are electrically connected to ground, so that electrons are ejected from the drain region 122 through the gate insulator 128 into the floating gate 126.
Because of the large interfacial barrier energy provided by the gate insulator 128, a charge stored onto the floating gate 126 has a long intrinsic storage time. For PMT""s of the type shown in FIG. 1, the measured mean decay of a stored potential (Vth) may be about 0.2V/decade-hours at 160xc2x0 C. Assuming an initial programmed mean Vth of about 8V, it would require about 1021 years for the PMT to discharge to a Vth of 3V. At the end of ten years, the leakage would have dropped to an average of one electron per day. Vth degradation in the PMT 110 is the result of and limited by physical processes. The magnitudes of the electric field and temperature dictate what conduction processes will be dominant. There are three distinct phases of Vth degradation for nominal PMT""s, each associated with a different possible physical mechanism of charge distribution/conduction and each having its own empirical xe2x80x9cactivation energy.xe2x80x9d First there is an initial period of rapid Vth loss, which is believed to be associated with the depolarization/dielectric absorption behavior observed to a lesser or greater degree in all capacitor dielectrics. Second, there is an intermediate period of charge loss associated with a high (but less than 6 Mvolt/cm, where Fowler-Nordheim tunneling is dominant) but decaying electric field. It is possible that there is movement of trapped electrons during this intermediate period, which has an xe2x80x9cactivation energyxe2x80x9d of about 0.2 eV. Ultimately, there is a long period of low field leakage through the gate insulator. The low field conduction mechanism is generally accepted as being conduction by thermionic emission.
When subjected to elevated temperatures, e.g., 160xc2x0 C. or more, PMT""s experience a significant initial drop in Vth attributed to the first degradation phase noted above. Thereafter, Vth stabilizes, though continuing to drop at a much lower rate attributed to the second and third degradation phases noted above. This lower rate is sufficiently low to permit the reliability of the device to be judged based on the initial Vth drop. Accordingly, PMT""s typically undergo a data retention bake, or stress test, that involves baking at a sufficiently high temperature to cause the initial drop in Vth. A PMT is deemed to have passed the stress test if its Vth has not dropped below a predetermined level at the completion of the high temperature bake.
From the above, it can be appreciated that PMT""s capable of exhibiting more stable Vth, corresponding to improved reliability and memory retention time, would be desirable. It would also be desirable to eliminate the requirement for a stress test to ascertain reliability of a PMT.
The present invention is directed to a programmable memory transistor (PMT) that exhibits significantly better performance in terms of charge retention and reliability. The PMT of this invention is able to make use of a single polysilicon layer, and is capable of memory retention times of five orders of magnitude greater than similar single-polysilicon PMT""s. The PMT also provides improved testability as a result of a greater measurement sensitivity for defects.
The PMT of this invention generally comprises an insulated gate field effect transistor (IGFET) and a capacitor structure on a semiconductor substrate. The IGFET comprises source and drain regions in a surface of the substrate, a channel between the source and drain regions, a gate insulator overlying the channel, and a first floating gate on the gate insulator. The capacitor structure comprises a lightly-doped well of a first conductivity type in the surface of the substrate, a heavily-doped first diffusion of the first conductivity type in the lightly-doped well, and a second diffusion of a second conductivity type in the lightly-doped well and spaced apart from the first diffusion so as to define therebetween a surface region of the lightly-doped well. The capacitor structure further comprises a control gate insulator that overlies the surface region of the lightly-doped well, a second floating gate on the control gate insulator, and a conductor in ohmic contact with the lightly-doped well through the first diffusion and in further contact with the lightly-doped well through the second diffusion. The first and second floating gates are electrically connected, preferably as a result of being formed of the same polysilicon layer, to maintain the first and second floating gates at the same potential.
As a result of the above structure, the second floating gate is capacitively coupled to the lightly-doped well through the control gate insulator so as to define a control gate for the first floating gate. As such, a sufficient voltage can be applied to the lightly-doped well to cause ejection of electrons from the drain region of the insulated gate field effect transistor and trap some of the ejected electrons in the first floating gate. According to the invention, PMT""s fabricated with the oppositely-doped diffusions as described above do not experience the initial drop in Vth that occurs with conventional single-polysilicon PMT""s when exposed to elevated temperatures, e.g., during a data retention bake. As such, the PMT of this invention is capable of far superior data retention over comparable single-polysilicon PMT""s. An additional benefit of the invention is the ability to simplify and/or shorten the aforementioned stress test performed on conventional PMT""s to evaluate device reliability on the basis of the initial Vth drop.
Other objects and advantages of this invention will be better appreciated from the following detailed description.